Record speed compensation for systems for processing recorded information



Jan. 6, 1970 w. F. GUNNlNG ETAL filfiilf RECORD SPEED COMPENSATION FORSYSTEMS FOR PROCESSING RECORDER INFORMATION 3 Sheets-Sheet 2 Filed May24. 1965 W---- mm N. M T mm x mm a p. m 0 P P r A! P r N. a .2 3 rm :4 A9 a w y 3% f aw 1 1|: 1. n a N a W m L e a n 1 M P m an a 7). MG w Wm wT V 2 v m a T1 I 0 R AF w 4 AW WI 0 Illlllllllul'll I llilllllllul. )m Mw J F 5 w. J 1 fi m W n m-mxwm HQ? 35. u 2 .52 2.. f MM g m 2 irlliL u wi l. mw 1 a M o h. m 4 5 r, 9 V: 0 P- A [w 7 4 4 i T 5 W. M. 4 5 f M u IQ a ii... a m r w 2 4/; A f e w P W fir J f m m u H ml 7M 0/, a o a n ww J. W u lllrlfziesilllL 0 W 0 llll 1.. 0 #3 m m W w Jan. 6, 1970 w-. F.GUNNING ETAL 3,488,452

RECORD SPEED COMPENSATION FOR SYSTEMS FOR PROCESSING RECORDERINFORMATION Filed May 24, 1965 s Sheets-Sheet s u/v/vm/G 1? GLEN DSEN ww W 6 K OPE N 1 GOP firm/ave Yr.

United States Patent RECORD SPEED COMPENSATION FOR SYSTEMS FORPROCESSING RECORDED INFORMATION William F. Gunning, Fullerton, and R.Glen Madsen,

Newport Beach, Calif., assignors to Astrodata, Inc.,

Anaheim, Calif., a corporation of California Filed May 24, 1965, Ser.No. 458,209 Int. Cl. G11b /00 US. Cl. 179-1001 14 Claims ABSTRACT OF THEDISCLOSURE The disclosure concerns frequency domaintape speedcompensation wherein overall stability for a given channel is related tothe stability of the data discriminator alone, as compared withconventional systems wherein the overall stability is related to the sumof the stabilities of both the data discriminator and the referencefrequency discriminator.

This invention relates generally to the processing of time or frequencymodulated signals, and more particularly concerns improvements insystems providing compensation for errors in playback speed of arecording from which the FM data input signal is derived.

Frequency multiplexed FM instrumentation systems employ a recording, asfor example magnetic tape, on which a multiplex of frequency modulatedsub-carrier signals are recorded along with a reference frequencysignal. Upon playback of the tape, the sub-carrier signals are separatedby band pass filters and applied to FM subcarrier discriminators toderive signals representing the data in variable voltage form. Incertain systems of this type, for example as disclosed in US. Patent3,017,616 to Runyan, a reference frequency is converted to a voltage andapplied to a data discriminator in biasing relation in order tocompensate for record playback speed error; however, unwanted errors andother disadvantages arise and are associated with such prior systemswhere reference frequency to error voltage conversion is employed. Suchprior systems may be characterized as employing analog domain tape speedcompensation.

It is a major object of the present invention to eliminate theabove-mentioned and other difsa'dvantages of prior record speedvariation compensation" methods and systems, through the provision 'ofajjnovelfand unusual system wherein a version of the referencedrequencyis directly employed to obtain compensation, the present systemcharacterized as employing frequency domain tape speed compensation. Asa result, the overall stabilityfor a given data channel is. that of thedata discriminator alone, whereas in conventional lit St n s the overallst'abil. ity is the sum of the stabilities of both" the datadiscriminator and the reference frequency discriminator,

In a system employing the piesent invention, a frequency modulated datainput signal i is recorded, as for example on magnetic tape, alongwith areference frequency signal f During playback, frequencies f f andversions 1'', and fg'vary proportionally with tape speed variations;further the system incorporates data discriminator means responsive to.the fa and f,,' signals. to derive an internal or feedback signal offrequency] tracking and an output voltage that varies as a function ofthe ratio f /f As a result, thediscriminator output voltage is notaffected by tape speed changes, up to the limit that the data andreference frequency delays can be matched, since such changesmerelyincrease or decrease ea'chof f, and f, by the same proportion, whichcancel in the ratio f /f Another important object of the invention is toprovide 3,488,452 Patented Jan. 6, 1970 means responsive to the recordedreference signal of frequency f, to supply a version thereof offrequency i to the data discriminator. Such a means typically includes aband pass filter and a phase locked loop respectively characterized asproviding time delays T1 and T2 for the reference signol version offrequency i further, the data discriminator includes a band pass filtercharacterized as providing a time delay 7'4 for the data input signal offrequency i and in certain circumstances the sum of T1 and 1' issubstantially equal to 1 Under certain other circumstances, as willappear, it is important to provide an additional time delay 7'5 for thereference frequency version "being supplied to the data discriminator,such additional time delay being supplied by an auxiliary phase lockedloop in the data discriminator. In this event, the data signal f isgiven delay T5 by an external delay line such that 7' equals 1' plus T2,and T equals T4. Another function of the auxiliary phase locked loop isto convert the reference signal version of frequency f, to anappropriate clocks signal of frequency f supplied to the currentcontrolled oscillator (ICO) in the main phase locked loop of the datadiscriminator.

These and other objects and advantages of the invention, as well as thedetails of illustrative embodiments, will be more fully understood fromthe following detailed description of the drawings in which:

FIG. 1 is a block diagram showing a data handling system embodying theinvention;

FIG. 2 is a block diagram showing a data discriminator usable in theFIG. 1 data handling system;

FIG. 3 illustrates the use of a current controlled oscillator in themain phase locked loop of the data discriminator;

FIG. 4 is a more detailed showing of the auxiliary or referencefrequency delay loop of the data discriminator;

FIG. 5 is Bode diagram of the auxiliary loop filter;

FIG. 6 is a Bode diagram of the VCO response in the auxiliary loop;

FIG. 7 is a Bode diagram of the complete open loop transfer function, asrespects the auxiliary loop; and

FIG. 8 is a showing like that of FIG. 4, but directed to a modified formof the reference frequency delay'loop.

Referring first to FIG. 1, the system for handling recorded informationcomprises a magnetic tape playback device 10 such as a drive and atransducer operable to translate film or tape signals recorded onmagnetic tape into'time varying electrical signals, the latter typicallyinclude frequency modulated sub-carrier signals as well as a referencefrequency signal. The reference frequency is preferably but notnecessarily recorded on the same track with the FM data multiplex, i.e.the reference frequency 1, may be recorded on a track different from thedata multiplex.

The FIG. 1 system includes data discriminator channels 11 correspondingto the number of sub-carrier signals to be handled at one time, thechannels being connected in parallel and to the output of playbackdevice 10 through as nitable delay line 12. Each discriminator channelincludes a data discriminator 13 typically incorporating a band passfilter 14, better seen in FIG. 2, for rejecting signals having afrequency outside the channel pass band. The diagrams show the datasignal of frequency f applied to a typical data discriminator 13, thissignal falling within the band passed by the filter. As will apepar, thedata signal of frequency f is time delayed in the conventional delayline 12 by an amount T3, and is also time delayed in the conventionalband pass filter 14 by an amount T4.

The FIG. 1 system also includes a reference frequency channel 15 inwhich the reference signal of frequency 1, obtained from the recording10 is processed, as by unit 16. In the latter the reference frequency f,is separated from the FM multiplex by a band pass filter 17 having anenvelope delay T1. The reference frequency signal 1, is then convertedin unit 16 to a new frequency f,, i.e. a frequency version of thereference frequency which is suitable for application to the wow andflutter input at 18 of the data discriminator 13. The conversion processis typically implemented by passage of the reference frequency 7,through limiter 20 seen in FIG. 2 and application to a phase locked loop21 connected with suitable frequency dividers 22 and 23 arranged so thatthe reference frequency version f is proportional to f and typicallyequals where m and 11 represent the division factors in the dividers 22and 23.

Loop 21 typically includes a phase detector 24, loop filter 25 tocontrol the response of the loop, including phase and gain, and aconventional voltage controlled oscillator 26 connected as shown. TheVCO output frequency is divided by a factor m at 22 and applied todetector 24. In the frequency conversion process the reference frequencyis delayed by an additional time T2 determined by the design of the loop21 so that reference frequency version 1, is delayed by the total amountT1+T2.

Referring again to the data discriminator 13, it is responsive to the fand 1, input signals to derive an internal or feedback signal offrequency f tracking f ,and also to derive an output voltage that variesas a function of the ratio f /f as will be seen. As a result, thediscriminator phase locked loop output voltage E is not affected by tapespeed changes, since such changes merely increase or decrease each of iand f by the same proportion, which cancel in the ratio Morespecifically, the data discriminator 13 typically includes a main phaselocked loop 27 responsive to the input data signal of frequency f thathas passed through band pass filter 14, limiter 14a, and an auxiliaryphase locked loop 28 to which the above described version of thereference frequency signal of frequency f, is supplied at 18. Auxiliaryloop 28 typically converts the version f to a clock signal of frequencyf suitable for application to the main loop 27. In addition, theauxiliary loop 28 provides a time delay T5 for the clock signal i tomatch the delay 1' of the data signal f Elements of the loop 28, includethe phase detector 30, loop filter 31 to control the response of theloop, and a conventional voltage controlled oscillator or V 32, anddivider 33 to divider the VCO output frequency f for application to thedetector 30. The arrangement is such that the clock frequency version fat the output of the VCO 32 is proportional to and to f,, and typicallyequals where m and 12 again represents the division factors in dividers22 and 23 and p represents the division factor in the divider 33.

The phase delays r through 7'5 discussed above are typicallyinterrelated in such manner that the data signal of frequency f and theclock signal of frequency f are time correlated at the respective inputs35 and 36 of the main loop 27 of the data discriminator. Theinterrelation of the delays may be grouped as follows, according todifferent design circumstances, the objective in each case being toprovide means for delaying f by an amount to match the delay encounteredby f T1+Tz=7a 74 75 1+ 2+ a+ s Referring now to the main loop 27, ittypically includes a phase detector 38 and loop filter 39 which may haveconventional design, and a current controlled oscillater 40 as describedin Stanley C. Forrest, Jr. et al. application, Voltage ControlledOscillator, Ser. No. 424,558. Such an oscillator is shown in the loop27a of FIG. 3 herein to include a. charge storage capacitor 41, asumming junction 42 connected at 43 with the capacitor 41, a firstunidirectional current flow leg indicated generally at 44 and connectedto junction 42 to provide a path for charge current 1,, a secondunidirectional current flow leg 45 and connected to junction 42 toprovide a path for discharge current I and a third leg or lead indicatedat 27 and connected to junction 42 to provide a path for variablecurrent 1,, obtained from the loop filter. Network leg 44 is shown toinclude an appropriate resistor 49 and diode 50, suitable positive andnegative voltage sources 51 and 52 being connected to the respectivelegs 44 and 45.

The sum of the currents at junction 42 is represented by the expressions(I,,--I or (l -l -l-l depending upon whether a switching device 53 for Iis set or reset. Device 53, which is connected to leg 44 via diode 54,functions to periodically shunt or interrupt flow of I, current tojunction 42 over timewise spaced intervals, the latter being establishedas a result of the i clock pulse input to device 53 operating inconjunction witth trigger pulse inputs at 55 from a comparator 56, asdescribed in detail in said Forrest et a1. application. Suffice it tosay herein that the comparator output signal of frequency is defined bythe following equation:

rfv

f In FIG. 3, I is seen as derived from the output volt-age E impressedon resistor 58 of resistance R so that Equation 10 may be written:

If: 'M.) (113:)

Moreover, since f is directly proportional to f (say f =f we can rewrite11a as:

fi e 'M.) (11b) Now, inasmuch as f is proportional to f,, the followingequation may be written from what has been stated previously:

With tape or record speedvariation, Equation 12 may be rewritten asfollows:

5 where e is the variable wow and flutter fractional increase ordecrease in tape or record speed. Further, Equation 11a may then bewritten as follows:

The error output of the phase detector 38 may be constant expressed asro= where 5 and & are the respective phase angles of the signals offrequency f and f constituting the inputs to the phase detector.

Accordingly, it is seen that the quantities (1+6) cancel in Equation 14;that perfect wow and flutter compensation result for any fixed frequencyin the subcarrier band from lower bandedge to upper bandedge; that I andE, remain constant; and that E may vary as a function of the ratio f /fwhere Finally, the output voltage E from loop 27 is typically applied tolow pass output filter 80 and amplifier 81, with feedback at 82, as seenin FIG. 2.

, Referring now to the auxiliary loop 28 in the data discriminator 13,it is redrawn in FIG. 4 to indicate the network of loop filter 31. Asillustrated, the network includes three branches 60, 61 and 62 connectedin parallel between phase detector 30 and the VCO 32. Branch 60 containsa capacitance 65 connected in series between terminals 63 and 64; branch61 has resistance 66 and capacitance 67 connected in series betweenterminals 63 and 64; and branch 62 has an amplifier 68 connected betweenthose terminals. Considering the loop 28, a Bode diagram of the loopfilter 31 is shown in FIG. 5, a Bode diagram of the VCO 32 response isshown in FIG. 6, and the Bode diagram of the complete open loop transferfunction KG(s) vs. frequency is shown in FIG. 7, KG(s) being defined asfollows:

where K phase detector constant, G (s)=transfer function of the filter31, K =amplifier constant,

K =VCO constant,

G (s)=VCO transfer function, and s:arbitrary complex variable.

Considering the loop 28 as a whole, the closed loop frequency tofrequency transfer function may be expressed in LaPlace notation asfollows: (C very much greater than C C =capacitance 65 R =resistance 66Note the absence of a zero term in the numerator of Equation 18.Equation 18 may be rewritten as follows:

where f: 1 /2w R C The roots of Equation 19 can be shown to be a pair ofcomplex conjugate poles which lie on. a circle of radius w in thenegative half of the complex plane, and at angles and from the negativereal axis such that =cos The normalized delay for w l is thenapproximately 2g. Further, the delay T5 of the loop 28 in simplifiedform is then as follows:

where ca is the corner frequency of the loop response and is the dampingfactor. If T4 is the delay encountered by the data in passing throughband pass filter 14 in the discriminator 13, then appropriate values ofto and may be selected to make T5 equal to T4 in each datadiscriminator, to implement Case 1 above. Thus, means is provided tocontrol the delay and damping factor for optimal magnitude and timedelay.

FIG. 8 shows another form of the auxiliary loop discriminator, thedifference in the loop filter includes parallel branches 71 and 72 eachconnected between the phase detector output terminal 73 and the VCO 32.Branch 71 includes resistance 75 and capacitance 76, and branch 72includes capacitance 77. Amplifier 74 is connected between terminal 73and the VCO 32.

Phase detectors 24, 30 and 38 and loop filters 25, 31 and 39 may beadvantageously mechanized as disclosed in Edward K. Dalton applicationfor U.S. Letters Patent entitled, FM Discriminator Smoothing Network,Ser. No. 441,183, filed Mar. 19, 1965-, now Patent No. 3,399,352.

We claim:

1. In a system for processing a time domain modulated data input signalof frequency f recorded with a reference frequency signal characterizedin that the signal frequency f and a frequency version of the referencesignal of frequency f vary with record speed variations, datadiscriminator means response to the f and f signals to derive aninternal signal of frequency 1, tracking f and an output voltage E saidmeans including a main phase locked loop comprising a phase detector toreceive f signal, a loop filter connected to receive the phase detectoroutput and a current controlled oscillator connected to receive currentI from the loop filter and said f signal and to produce said f signalalso applied to said phase detector, f varying directly as I and 12,.

2. The system of claim 1 including means responsive to the recordedreference signal of frequency f to supply a preliminary frequencyversion thereof of frequency i to said data discriminator.

3. The system of claim 2 in which said last named means includes a bandpass filter and a phase locked loop respectively characterized asproviding envelope delays 7'1 and T2 for the reference signal frequencyversion of frequency f 4. The system of claim 3 in which the datadiscriminator includes a band pass filter characterized as providing anenvelope delay T4 for the data input signal of frequency f 5. The systemof claim 4 in which the sum T1+T2 is substantially equal to T4.

6. The system of claim 3 including a delay line electrically connectedat the input side of the data discriminator to provide an additionalphase delay 7'3 for the data input signal of frequency i and furthercharacterized in that the sum T1+T2 is substantially equal to T 7. Thesystem of claim 4 including a delay line electrically connected at theinput side of the data discriminator to provide an additional envelopedelay T3 for the data input signal of frequency i and furthercharacterized in that the sum 1- is substantially equal to the sum 1-4-1 8. The system of claim 7 in which the data discrimlnator includesan auxiliary phase locked loop through which a frequency version of thereference frequency signal of frequency is supplied to the main phaselocked loop.

9. The system of claim 8 in which the auxiliary phase locked loopincludes means to convert the reference signal version of frequency f toa clock signal of frequency the auxiliary loop providing an envelopedelay 7' for the clock signal of frequency f 10. The system of claim 9in which the sum T1+T2+15 is substantially equal to the sum 7 4-7 11. Ina system for processing a time domain modulated data input signalrecorded with a reference frequency signal characterized in that thedata signal and reference signal are both subject to wow and flutterduring recording and playback, a reference channel including a firstphase locked loop to convert the reference frequency to a time delayedversion f and a data discriminator to receive the data signal and towhich said version i is applied as a control such that the discriminatorhas an otuput voltage signal that does not vary with said wow andflutter, the data discriminator including a main phase locked loop toreceive the data signal, and an auxiliary phase locked loop to receiveand convert said version i to a further time delayed clock frequency fapplied as a reference and control to said main phase locked loop, theauxiliary phase locked loop including a phase detector to receive saidversion i a loop filter connected to receive the phase detector output,a voltage controlled oscillator connected to receive the loop filteroutput, and a frequency divider to receive and divide the oscillatoroutput frequency j and to supply said divided frequency to the phasedetector.

12. The combination of claim 11 in which the loop filter includes twoparallel branches, one containing resistance and capacitance in seriesand the other containing capacitance only.

13. In a system for processing a frequency modulated data input signalrecorded with a reference frequency signal characterized in that thedata signal and reference signal are both subject to wow and flutterduring recording and playback, a reference channel including a firstphase locked loop to convert the reference frequency to a time delayedfrequency version f and a data discriminator to receive the data signaland to which said frequency version is applied as a control such thatthe discriminator has an output voltage signal that does not vary withsaid wow and flutter, the data discriminator including a main phaselocked loop to receive and convert said reference frequency version i toa further time delayed clock frequency f applied as a reference andcontrol to said main phase locked loop, the main phase locked loopincluding a phase detector to receive the data signal, a loop filterconnected to receive the phase detector output, and a current controlledoscillator connected to receive current from the loop filter and saidclock frequency f as an oscillator control and to produce a feedbacksignal of frequency f tracking the data signal frequency, thediscriminator loop output being derived as a voltage E from said loopfilter.

14. The combination of claim 13 in which E, is related to i and f by theequation where x and 5 are constants, and :1: is the fractional changein the recording playback speed.

References Cited UNITED STATES PATENTS 3,181,133 4/1965 Seitner340-174.1 3,017,616 1/1962 Runyan 340-1741 3,253,237 5/1966 Runyan179100.2

BERNARD KONICK, Primary Examiner I. RUSSELL GOUDEAU, Assistant ExaminerUS. Cl. X.R. 340-174.1

